Top-down modeling of RISC processors in VHDL
نویسندگان
چکیده
In this report, we present a top-down VHDL modeling technique which consists of two main modeling levels: speci cation level and functional level. We modeled a RISC Processor (RP) in order to demonstrate the feasibility and e ectiveness of this methodology. All models have been simulated on a SPARC 1 workstation using the ZYCAD VHDL simulator, version 1.0a. Experimental results show feasibility of the modeling strategy and provide performance measures of RP design features.
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تاریخ انتشار 1993